Traffic control systems have reached a high level of sophistication: they are general purpose machines that can, in principle, run any traffic control software. The firmware they are running turns them into special purpose machines able to operate only according to some pre-defined rules. The firmware usually allows limited customizations through parameters, but it does not support the introduction of new control schemes. As a result, implementing a new traffic control scheme requires the re-implementation of the firmware, a complex task given the low-level programming required. The complexity of the task has created a rift between the academic community and the roadside equipment manufacturers’ community. As a result, the traffic control firmware does not benefit from the work and novel ideas of the academic community and it is often suboptimal when it comes to issue of interoperability, integration and cost-effectiveness. At the same time the efforts of the academic research are often wasted by an incorrect understanding of the underlying system: many sophisticated control schemes proposed by the researcher are never used because they are not implementable over the existing hardware. This paper introduces a software suite, the Tools for the development of Traffic Control Systems (TTCS), meant to bridge the gap between these two communities. The key concept is the introduction of the Control logic / Hardware Abstraction Layer (CHAL) between the control logic and the hardware, reducing the complexity of developing a new traffic control scheme. It enables the control designer to re-use the code developed in the design, testing and simulation phases directly on the traffic controller. Conforming to the CHAL architecture ensures that the design is implementable over the target hardware. Moreover CHAL decouples the control logic and the hardware (ensuring software portability), easing both hardware and software upgrades (avoiding the need to update the software when the hw changes and vice versa). A software library for the integration of Quadstone Paramics 5.4 into the CHAL architecture is presented.
Abstract:
Publication date:
November 19, 2007
Publication type:
Journal Article
Citation:
Zennaro, M., & Sengupta, R. (2007). CHAL - Control logic / Hardware Abstraction layer. https://escholarship.org/uc/item/9ff3q0c0